71. G. S. Lin and J. B. Kuo, “Fringing-Induced Thin-Channel-Impact (FINCE) Associated Capacitance Choices regarding Nanometer FD SOI NMOS Equipment Playing with Mesa-Isolation Via three-dimensional Simulation” , EDSM , Taiwan ,
72. J. B. Kuo, “Progression off Bootstrap Techniques in Reduced-Voltage CMOS Digital VLSI Circuits to have SOC Software” , IWSOC , Banff, Canada ,
P. Yang, “Gate Misalignment Feeling Associated Capacitance Choices away from a 100nm DG FD SOI NMOS Equipment which have letter+/p+ Poly Most readily useful/Bottom Door” , ICSICT , Beijing, China
73. G. Y. Liu, Letter. C. Wang and J. B. Kuo, “Energy-Effective CMOS Highest-Stream Rider Circuit to the Complementary Adiabatic/Bootstrap (CAB) Technique for Reasonable-Fuel TFT-Lcd Program Applications” , ISCAS , Kobe, The japanese ,
74. Y. S. Lin, C. H. Lin, J. B. Kuo and you may K. W. Su, “CGS Capacitance Occurrence out of 100nm FD SOI CMOS Devices having HfO2 High-k Gate Dielectric Considering Vertical puerto rican brides and you can Fringing Displacement Outcomes” , HKEDSSC , Hong-kong ,
75. J. B. KUo, C. H. Hsu and you may C. P. Yang, “Gate-Misalignment Associated Capacitance Choices regarding a great 100nm DG SOI MOS Gizmos that have Letter+/p+ Top/Bottom Door” , HKEDSSC , Hong kong ,
76. G. Y. Liu, N. C. Wang and J. B. Kuo, “Energy-Productive CMOS Highest-Load Driver Circuit for the Complementary Adiabatic/Bootstrap (CAB) Technique for Lowest-Power TFT-Liquid crystal display Program Software” , ISCAS , Kobe, Japan ,
77. H. P. Chen and you may J. B. Kuo, “A great 0.8V CMOS TSPC Adiabatic DCVS Reasoning Routine on Bootstrap Strategy to own Lower-Fuel VLSI” , ICECS , Israel ,
B. Kuo, “A novel 0
80. J. B. Kuo and you may H. P. Chen, “The lowest-Voltage CMOS Load Driver to your Adiabatic and you can Bootstrap Strategies for Low-Fuel System Software” , MWSCAS , Hiroshima, The japanese ,
83. M. T. Lin, Age. C. Sunrays, and J. B. Kuo, “Asymmetric Entrance Misalignment Effect on Subthreshold Functions DG SOI NMOS Devices Considering Fringing Digital Field-effect” , Electron Gizmos and you will Thing Symposium ,
84. J. B. Kuo, Elizabeth. C. Sunrays, and you will Yards. T. Lin, “Investigation regarding Gate Misalignment Influence on brand new Threshold Current from Twice-Gate (DG) Ultrathin FD SOI NMOS Gadgets Using a tight Model Considering Fringing Digital Field-effect” , IEEE Electron Gizmos to own Microwave oven and you can Optoelectronic Apps ,
86. E. Shen and you may J. 8V BP-DTMOS Blogs Addressable Memories Cell Routine Produced by SOI-DTMOS Techniques” , IEEE Appointment to your Electron Gadgets and you can Solid state Circuits , Hong kong ,
87. P. C. Chen and you can J. B. Kuo, “ic Reason Routine Playing with a direct Bootstrap (DB) Technique for Low-voltage CMOS VLSI” , Global Symposium for the Circuits and you may Systems ,
89. J. B. Kuo and you may S. C. Lin, “Lightweight Dysfunction Model for PD SOI NMOS Devices Offered BJT/MOS Impression Ionization to own Spruce Circuits Simulator” , IEDMS , Taipei ,
ninety. J. B. Kuo and you can S. C. Lin, “Compact LDD/FD SOI CMOS Equipment Design Provided Energy Transport and you may Mind Heating for Liven Routine Simulation” , IEDMS , Taipei ,
91. S. C. Lin and J. B. Kuo, “Fringing-Created Hindrance Decreasing (FIBL) Outcomes of 100nm FD SOI NMOS Gizmos with a high Permittivity Entrance Dielectrics and you can LDD/Sidewall Oxide Spacer” , IEEE SOI Fulfilling Proc , Williamsburg ,
ninety five. J. B. Kuo and you may S. C. Lin, “The new Fringing Electric Field-effect for the Brief-Station Impact Tolerance Voltage out-of FD SOI NMOS Equipment which have LDD/Sidewall Oxide Spacer Design” , Hong-kong Electron Gizmos Meeting ,
93. C. L. Yang and you can J. B. Kuo, “High-Heat Quasi-Saturation Model of Large-Voltage DMOS Stamina Devices” , Hong-kong Electron Equipment Appointment ,
94. Age. Shen and you may J. B. Kuo, “0.8V CMOS Articles-Addressable-Thoughts (CAM) Phone Ciurcuit which have an instant Level-Contrast Effectiveness Using Majority PMOS Active-Endurance (BP-DTMOS) Method Centered on Standard CMOS Tech to have Reduced-Voltage VLSI Assistance” , Worldwide Symposium into the Circuits and you can Solutions (ISCAS) Legal proceeding , Washington ,